PLC arithmetic reference examples — verification scope

Source material
  The user-supplied JPEG sheets:
  77회_1일차_2과제_page-0001.jpg
  77회_2일차_2과제_page-0001.jpg
  77회_3일차_2과제_page-0001.jpg
  79회_2일차_2과제_page-0001.jpg
  79회_3일차_2과제_page-0001.jpg

These are editable reference interpretations, not official examination answers.
The examples contain only ordinary web editor cells and native APP instructions.
No JavaScript predicate substitutes for PLC logic during the tests.

Executable artifact
  exam-arithmetic.js exports PlcExamArithmetic for browsers and module.exports
  for Node. examples contains {id, title, program, description, notes}.
  build(id) creates a fresh version-1, eight-column ladder program.
  tests/plc-exam-arithmetic.test.js executes the actual shipped WebAssembly core.
  Current verification: nine tests, five native compile checks and 27 behavioral
  scenarios. Timelines sample 100ms, the T0 timer's native base.

Common terminals
  PB-A/B/C: P00/P01/P02 (native X0/X1/X2).
  SS-A/B/C: P03/P04/P05 (native X3/X4/X5).
  PL-A/B/C/D/E: P20/P21/P22/P23/P24 (native Y0..Y4).
  Task 2 selection: SS-A OFF and SS-B ON.
  PB value entry uses falling edges, so a held button increments only on release.
  Counts are held while a valid operation is active.
  D0/D1/D2 contain entered A/B or N/M/K counts; M100 is operation-active.

77-1-2
  Verified (A,B): (2,3), (1,4), (1,1), (2,2).
  First second: lamps A and A+B.
  Second second: lamps strictly between those endpoints, matching the drawn
  traces. A/B clear on completion to permit the next drawn input sequence.
  Each input caps at four and their combined total caps at five.
  Additional checks cover held input, B=0 rejection, excess input, mode-off
  reset, and preventing a stale start after the mode is re-enabled.
  SS-C uses its ON state as reset, as specified without an edge qualifier.

77-2-2
  Verified (n,m): (3,9), (2,6), and odd-average case (1,2).
  PL-A or PL-B selects the nearer value to R=5, for n or m seconds.
  PL-C uses the smaller absolute distance, PL-D the rounded mean.
  PL-E rounds abs(5 - the exact mean). It does not subtract an already rounded
  mean: for (1,2), PL-D=2s and PL-E=4s.
  Values survive completion and PB-C can immediately replay them.
  Additional invalid cases: (0,1), (5,1), (3,3), (3,7).
  SS-C rising edge or task-off clears the program state.

77-3-2
  Verified (N,M,K): (2,7,3), (4,3,2), (2,1,5).
  PL-A/B/C chooses the unique value closest to R=6 and stays on for that
  entered value in seconds. PL-D lights for the rounded mean in seconds.
  PL-E blinks exactly the rounded mean count.
  Blink period is interpreted from the drawing as 0.5s ON / 0.5s OFF,
  starting ON. The tests check every 100ms sample, not merely the final count.
  Additional invalid cases: (4,8,1), (6,2,3), (0,2,3).
  SS-C rising edge starts; falling edge clears all entered values and outputs.

79-2-2
  Verified (A,B): (1,5), (2,3), (3,1), (4,1), (5,1), (14,10).
  DIV computes A modulo 5; remainders 1/2/3/4/0 select A/B/C/D/E.
  The selected lamp stays on for B seconds.
  Tests cover all five remainder classes, the displayed larger 14/10 case,
  a held start that must not retrigger, and SS-C reset.

79-3-2
  Verified (N,M,K): (4,1,2), (1,3,2), (1,2,4).
  The maximum selects one of PL-A/B/C until SS-C falls.
  PL-D stays on for maximum seconds; PL-E blinks maximum times with the same
  0.5s ON / 0.5s OFF interpretation as above.
  SOURCE AMBIGUITY: the graph's right-hand annotations say A=K and C=N;
  the bottom condition table says A=N and C=K. This program follows the
  bottom table: A=N, B=M, C=K. The visible (1,3,2) example has M maximal
  and therefore cannot disambiguate the contradictory labels.

Limits
  These checks demonstrate five arithmetic task-2 examples. They do not by
  themselves verify every attached sheet or certify examination correctness.
  They use 16-bit integer arithmetic and a 100ms elapsed timer. Behavioral
  verification covers the concrete counts above (maximum entered count 14);
  large-count overflow, counts near register limits, and durations >=3276.7s
  are not claimed verified. The PLC engine provides wider arithmetic for a
  separately designed program if such ranges are needed.
  Reset and edge ordering are scanned PLC semantics. Simultaneous user events
  that the paper does not specify were not used to invent additional rules.
  No native runtime changes were needed for these verified scenarios.
